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semiconductor group 1 1.96 ? 4 194 304 words by 4-bit organization ? 0 to 70 c operating temperature ? performance: ? single + 3.3 v ( 0.3v ) supply ? low power dissipation max. 396 active mw (hyb3117400bj/bt-50) max. 363 active mw (hyb3117400bj/bt-60) max. 330 active mw (hyb3117400bj/bt-70) max. 360 active mw (hyb3116400bj/bt-50) max. 324 active mw (hyb3116400bj/bt-60) max. 288 active mw (hyb3116400bj/bt-70) 7.2 mw standby (lv-ttl) 3.6 mw st andby (lv-cmos) 720 m w standby for l-version ? output unlatched at cycle end allows two-dimensional chip selection ? read, write, read-modify-write, cas -before-ras refresh, ras -only refresh, hidden refresh, self refresh and test mode ? fast page mode capability ? all inputs, outputs and clocks f ully ttl-com patible ? 2048 refresh cycles / 32 ms for hyb3117400 4096 refresh cycles / 64 ms for hyb3116400 ? plastic package: p-soj-26/24-1 (300 mil) p-tsopii-26/24-1 (300mil) -50 -60 -70 t rac ras access time 50 60 70 ns t cac cas access time 13 15 20 ns t aa access time from address 25 30 35 ns t rc read/write cycle time 90 110 130 ns t pc fast page mode cycle time 35 40 45 ns 3.3v 4m x 4-bit dynamic ram advanced information hyb3116400bj/bt(l) -50/-60/-70 hyb3117400bj/bt(l) -50/-60/-70
semiconductor group 2 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram the hyb 3116(7)400bj/bt is a 16mbit dynamic ram organized as 4194304 words by 4-bits. the hyb 3116(7)400bj/bt utilizes a submicron cmos silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. multiplexed address inputs permit the hyb 3116(7)400bj/bt to be packaged in a standard soj 26/24 300 mil or tsopii-26/24 300 mil wide plastic package. these packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. system-oriented features include single + 3.3 v ( 0.3 v) power supply, direct interfacing with high-performance logic device families.the hyb3116400btl parts have a very low power ?sleep mode supported by self refresh. ordering information type ordering code package descriptions hyb 3117400bj-50 p-soj-26/24-1 300 mil dram (access time 50 ns) hyb 3117400bj-60 p-soj-26/24-1 300 mil dram (access time 60 ns) hyb 3117400bj-70 p-soj-26/24-1 300 mil dram (access time 70 ns) hyb 3117400bt-50 p-tsopii-26/24-1 300 mil dram (access time 50 ns) hyb 3117400bt-60 p-tsopii-26/24-1 300 mil dram (access time 60 ns) hyb 3117400bt-70 p-tsopii-26/24-1 300 mil dram (access time 70 ns) hyb 3116400bj-50 p-soj-26/24-1 300 mil dram (access time 50 ns) hyb 3116400bj-60 p-soj-26/24-1 300 mil dram (access time 60 ns) hyb 3116400bj-70 p-soj-26/24-1 300 mil dram (access time 70 ns) hyb 3116400bt-50 p-tsopii-26/24-1 300 mil dram (access time 50 ns) hyb 3116400bt-60 p-tsopii-26/24-1 300 mil dram (access time 60 ns) hyb 3116400bt-70 p-tsopii-26/24-1 300 mil dram (access time 70 ns) hyb 3116400btl-50 p-tsopii-26/24-1 300 mil lp-dram (access time 50 ns) hyb 3116400btl-60 p-tsopii-26/24-1 300 mil lp-dram (access time 60 ns) hyb 3116400btl-70 p-tsopii-26/24-1 300 mil lp-dram (access time 70 ns)
semiconductor group 3 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram pin configuration pin names a0 to a10 row & column address inputs for hyb3117400 a0 to a11 row address inputs for hyb3116400 a0 to a9 column address inputs for hyb3116400 ras row address strobe oe output enable i/o1 -i/o4 data input/output cas column address strobe we read/write input v cc power supply (+ 3.3 v) v ss ground (0 v) n.c. not connected p-soj-26/24-1 (300mil) p-tsopii-26/24-1 (300mil) vcc i/o1 i/o2 we ras n.c. a10 a0 a1 a2 a3 vcc 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 vss i/o4 i/o3 cas oe a9 a8 a7 a6 a5 a4 vss hyb3117400bj/bt vcc i/o1 i/o2 we ras a11 a10 a0 a1 a2 a3 vcc 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 vss i/o4 i/o3 cas oe a9 a8 a7 a6 a5 a4 vss hyb3116400bj/bt
semiconductor group 4 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram block diagram for hyb3117400 no. 2 clock generator column address buffer(11) refresh controller refresh counter (11) address buffers(11) row no. 1 clock generator & data in buffer data out buffer column decoder sense amplifier i/o gating memory array 2048x2048x4 row decoder a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 we cas 2048 2048 x4 . ras 11 11 11 4 4 4 i/o1 i/o2 i/o3 i/o4 oe 11 11 a10
semiconductor group 5 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram block diagram for hyb3116400 no. 2 clock generator column address buffer(10) refresh controller refresh counter (12) address buffers(12) row no. 1 clock generator & data in buffer data out buffer column decoder sense amplifier i/o gating memory array 4096x1024x4 row decoder a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 we cas 4096 1024 x4 . ras 10 12 10 4 4 4 i/o1 i/o2 i/o3 i/o4 oe 12 12 a10 a11
semiconductor group 6 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram absolute maximum ratings operating temperature range ............................................................................................0 to 70 c storage temperature range.........................................................................................C 55 to 150 c input/output voltage ................................................................................-0.5 to min(vcc+0.5, 4.6) v power supply voltage.................................................................................................- 0.5 v to 4.6 v power dissipation.............................................................................................................. ...... 0.5 w data out current (short circuit) ............................................................................................... .50 ma note: stresses above those listed under absolute maximum ratings may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc characteristics (values in brackets for hyb3117400) t a = 0 to 70 c, v ss = 0 v, v cc = 3.3 v 0.3 v, t t = 5 ns parameter symbol limit values unit test condition min. max. input high voltage v ih 2.0 vcc+0.5 v 1) input low voltage v il C 0.5 0.8 v 1) ttl output high voltage ( i out = C 2 ma) v oh 2.4 C v 1) ttl output low voltage ( i out = 2 ma) v ol C 0.4 v 1) cmos output high voltage ( i out = C100 ua) v oh vcc-0.2 C v cmos output low voltage ( i out = 100 ua) v ol C 0.2 v input leakage current (0 v v ih vcc + 0.3v, all other pins = 0 v) i i(l) C 10 10 m a 1) output leakage current (do is disabled, 0 v v out vcc + 0.3v) i o(l) C 10 10 m a 1) average v cc supply current: -50 ns version -60 ns version -70 ns version (ras , cas , address cycling, t rc = t rc min.) i cc1 C C C 100(120) 90 (110) 80 (100) ma ma ma 2) 3) 4) 2) 3) 4) 2) 3) 4) standby v cc supply c urrent (ras =cas = v ih ) i cc2 C2maC
semiconductor group 7 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram average v cc supply current, during ras -only refresh cycles: -50 ns version -60 ns version -70 ns version (ras cycling: cas = v ih , t rc = t rc min.) i cc3 C C C 100(120) 90 (110) 80 (100) ma ma ma 2) 4) 2) 4) 2) 4) average v cc supply current, during fast page mode: -50 ns version -60 ns version -70 ns version (ras = v il , cas , address cycling, t pc = t pc min. ) i cc4 C C C 40 (40) 35 (35) 30 (30) ma ma ma 2) 3) 4) 2) 3) 4) 2) 3) 4) standby v cc supply current (ras = cas = v cc C 0.2 v) i cc5 C1 200 ma m a 1) l-version average v cc supply current, during cas - before-ras refresh mode: -50 ns version -60 ns version -70 ns version (ras , cas cycling, t rc = t rc min.) i cc6 C C C 100(120) 90 (110) 80 (100) ma ma ma 2) 4) 2) 4) 2) 4) average self refresh current (cbr cylce with tras>trassmin., cas held low, we =vcc-0.2v, address and din=vcc-0.2v or 0.2v) i cc7 _1 250 ma m a l-version capacitance t a = 0 to 70 c, v cc = 3.3 v 0.3v, f = 1 mhz parameter symbol limit values unit min. max. input capacitance (a0 to a10, a11) c i1 C5pf input capacitance (ras , cas , we , oe ) c i2 C7pf i/o capacitance (i/o1 - i/o4) c io C7pf dc characteristics (values in brackets for hyb3117400) t a = 0 to 70 c, v ss = 0 v, v cc = 3.3 v 0.3 v, t t = 5 ns parameter symbol limit values unit test condition min. max.
semiconductor group 8 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram ac characteristics 5)6) 16f t a = 0 to 70 c, v cc = 3.3 v 0.3 v, t t = 5 ns parameter symbol limit values unit note -50 -60 -70 min. max. min. max. min. max. common parameters random read or write cycle time t rc 90 C 110 C 130 C ns ras precharge time t rp 30 C 40 C 50 C ns ras pulse width t ras 50 10k 60 10k 70 10k ns cas pulse width t cas 13 10k 15 10k 20 10k ns row address setup time t asr 0C0C0Cns row address hold time t rah 8 C 10 C 10 C ns column address setup time t asc 0C0C0Cns column address hold time t cah 10 C 15 C 15 C ns ras to cas delay time t rcd 18 37 20 45 20 50 ras to column address delay time t rad 13 25 15 30 15 35 ns ras hold time t rsh 13 15 C 20 C ns cas hold time t csh 50 60 C 70 C ns cas to ras precharge time t crp 5C5C5Cns transition time (rise and fall) t t 350350350ns7 refresh period for hyb3117400 t ref C 32 C 32 C 32 ms refresh period for hyb3116400 t ref C 64 C 64 C 64 ms refresh period for l-version t ref C 256 C 256 C 256 ms read cycle access time from ras t rac C 50 C 60 C 70 ns 8, 9 access time from cas t cac C 13 C 15 C 20 ns 8, 9 access time from column address t aa C 25 C 30 C 35 ns 8,10 oe access time t oea C 13 C 15 C 20 ns column address to ras lead time t ral 25 C 30 C 35 C ns read command setup time t rcs 0C0C0Cns read command hold time t rch 0C0C0Cns11 read command hold time referenced to ras t rrh 0C0C0Cns11
semiconductor group 9 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram cas to output in low-z t clz 0C0C0Cns8 output buffer turn-off delay t off 0 13 0 15 0 20 ns 12 output buffer turn-off delay from oe t oez 0 13 0 15 0 20 ns 12 data to oe low delay t dzo 0C0C0Cns13 cas high to data delay t cdd 13 C 15 C 20 C ns 14 oe high to data delay t odd 13 C 15 C 20 C ns 14 write cycle write command hold time t wch 8 C 10 C 10 C ns write command pulse width t wp 8 C 10 C 10 C ns write command setup time t wcs 0C0C0Cns15 write command to ras lead time t rwl 13 C 15 C 20 C ns write command to cas lead time t cwl 13 C 15 C 20 C ns data setup time t ds 0C0C0Cns16 data hold time t dh 10 C 10 C 15 C ns 16 data to cas low delay t dzc 0C0C0Cns13 read-modify-write cycle read-write cycle time t rwc 126 C 150 C 180 C ns ras to we delay time t rwd 68 C 80 C 95 C ns 15 cas to we delay time t cwd 31 C 35 C 45 C ns 15 column address to we delay time t awd 43 C 50 C 60 C ns 15 oe command hold time t oeh 13 C 15 C 20 C ns fast page mode cycle fast page mode cycle time t pc 35 C 40 C 45 C ns cas precharge time t cp 10 C 10 C 10 C ns access time from cas precharge t cpa C30C35C40ns7 ras pulse width t ras 50 200k 60 200k 70 200k ns ac characteristics (contd) 5)6) 16f t a = 0 to 70 c, v cc = 3.3 v 0.3 v, t t = 5 ns parameter symbol limit values unit note -50 -60 -70 min. max. min. max. min. max.
semiconductor group 10 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram cas precharge to ras delay t rhpc 30 C 35 C 40 C ns fast page mode read-modify-write cycle fast page mode read-write cycle time t prwc 71 C 80 C 95 C ns cas precharge to we t cpwd 48 C 55 C 65 C ns cas -before-ras refresh cycle cas setup time t csr 10 C 10 C 10 C ns cas hold time t chr 10 C 10 C 10 C ns ras to cas precharge time t rpc 5C5C5Cns write to ras precharge time t wrp 10 C 10 C 10 C ns write hold time referenced to ras t wrh 10 C 10 C 10 C ns cas -before-ras counter test cycle cas precharge time t cpt 35 C 40 C 40 C ns test mode cas hold time t chrt 30 C 30 C 30 C ns write command setup time t wts 10 C 10 C 10 C ns write command hold time t wth 10 C 10 C 10 C ns self refresh cycle ras pulse width t rass 100k _ 100k _ 100k _ ns 17 ras precharge time t rps 95 _ 110 _ 130 _ ns 17 cas hold time t chs -50 _ -50 _ -50 _ ns 17 ac characteristics (contd) 5)6) 16f t a = 0 to 70 c, v cc = 3.3 v 0.3 v, t t = 5 ns parameter symbol limit values unit note -50 -60 -70 min. max. min. max. min. max.
semiconductor group 11 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram notes: 1) all voltages are referenced to vss. 2) icc1, icc3, icc4 and icc6 depend on cycle rate. 3) icc1 and icc4 depend on output loading. sp ecified values are measured with the output open. 4) address can be changed once or less while ras = vil. in the case of icc4 it can be changed once or less during a fast page mode cycle (tpc). 5) an initial pause of 200 m s is required after power-up followed by 8 ras cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cas-before-ras initialization cycles instead of 8 ras cycles are required. 6) ac measurements assume tt = 5 ns. 7) vih (min.) and vil (max.) are reference levels for measuring timing of input signals. transition times are also measured between vih and vil. 8) measured with a load equivalent to 100 pf and at voh=2.0 v (ioh = -2ma) , vol=0.8v (iol=2ma). 9) operation within the trcd (max.) limit ensures that trac (max.) can be met. trcd (max.) is specified as a reference point only: if trcd is greater than the specified trcd (max.) limit, then access time is controlled by tcac. 10)operation within the trad (max.) limit ensures that trac (max.) can be met. trad (max.) is specified as a reference point only: if trad is greater than the specified trad (max.) limit, then access time is controlled by taa. 11)either trch or trrh must be satisfied for a read cycle. 12)toff (max.) and toez (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13)either tdzc or tdzo must be satisfied. 14)either tcdd or todd must be satisfied. 15)twcs, trwd, tcwd, tawd and tcpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if twcs > twcs (min.), the cycle is an early write cycle and the i/o pin will remain open-circuit (high impedance) through the entire cycle; if trwd > trwd (min.), tcwd > tcwd (min.), tawd > tawd (min.) and tcpwd > tcpwd (min.) , the cycle is a read-write cycle and i/o pins will contain data read from the selected cells. if neither of the above sets of conditions is satisfied, the condition of the i/o pins (at access time) is indeterminate. 16)these parameters are referenced to the cas leading edge in early write cycles and to the we leading edge in read-write cycles. 17)when using self refresh mode, the following refresh operations must be performed to ensure proper dram operation: if row addresses are being refreshed on an evenly distributed manner over the refresh interval using cbr refresh cycles, then only one cbr cycle must be performed immediately after exit from self refresh. if row addresses are being refreshed in any other manner (ror - distributed/burst; or cbr-burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from self refresh.
semiconductor group 12 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram waveforms read cycle aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa row column row aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa valid data out ras cas address we oe i/o (inputs) i/o (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ras t rc t csh t rad t cas t rp t rah t crp t rsh t rcd t ral t asr t cah t asc t asr t rch t rrh t rcs t aa t oea t clz t cac t oez t odd t cdd t off t dzc t dzo t rac hi z hi z aaaa a aaa a aaa a aaa a aaa a aaa aaaa aaa a aaa a aaa a aaa a aaa a h or l wl1
semiconductor group 13 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram write cycle (early write) aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa ras cas address we oe i/o (inputs) i/o (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol . t ras t rc t csh t rad t cas t rp t crp t rsh t rcd t ral t asr t cah t asr aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa t cwl t rwl t wp t asc t wch valid data in t ds t dh hi z column aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa row row t rah t wcs aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa h or l wl2
semiconductor group 14 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram write cycle (oe controlled write) aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a valid data aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa t rwl t wp t oeh t odd t cwl aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa t dzo t oea t clz t ds t oez aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa t dh t rc aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa v ih v il row t dzc aaaa a aaa a aaa a aaa a aaa a aaa aaaa aaaa aaa a aaa a aaa a aaa a aaa a aaaa h or l hi-z hi-z column row t asc t rad t ral t cah t rah ras cas address we oe i/o (inputs) i/o (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol . t ras t csh t cas t rp t crp t rsh t rcd t asr t asr wl3
semiconductor group 15 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram read-write (read-modify-write) cycle aaa aaa aaa aaa aaa aaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa row row t csh t cas t crp t rwc t awd t asr t rp t ras t rah t cah i/o (outputs) v oh v ol v ih v il v ih v il i/o (inputs) oe we v ih v il t asr column t rcd t dh t rsh t rad t cwd t oeh t rwd t rwl t cwl t clz t wp t rcs t aa t oea t ds t dzc t dzo t odd t cac t oez valid data in data out t rac aaaa a aaa a aaa a aaa a aaa a aaa aaaa aaaa aaa a aaa a aaa a aaa a aaa a aaaa h or l t asc v ih v il v ih v il ras cas address v ih v il wl4
semiconductor group 16 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram fast page mode read cycle aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaa aaa aaa aaa aaa aaa aaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa t rasp t cas t cas t pc t cp t rcd t csh t cah t cah t asc t asc t asr t rah t rad t rcs t rcs t rcs t asc t cah t cas t rsh t crp t rp t asr t rch t cpa t oea t oea t aa t aa t dzc t dzc t cdd t rrh t cpa t oea t aa t dzc t dzo t odd t odd t dzo t odd t dzo t off t oez t oez t off t oez t cac t cac t clz t clz t clz t off t rac t cac va lid data out data out data out valid valid column column row row ras i/o (outputs) i/o (inputs) oe we address cas v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il aaaa a aaa a aaa a aaa a aaa a aaa aaaa aaaa aaa a aaa a aaa a aaa a aaa a aaaa h or l t rhcp t rch v oh v ol column fpm1
semiconductor group 17 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram fast page mode early write cycle aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a t ras t rp t rsh t cas t cas t cp t crp t ral t cah t asr t cwl t rwl t cah t asc t asc t cwl t cwl t wcs t wcs t wcs t wch t wp t wp t wch t wp t wch t rad t cas t rcd t pc t cah t rah t asr t asc t dh t ds t ds t dh t dh t ds column column column row valid data in valid valid data in data in column hi-z ras i/o (outputs) i/o (inputs) oe we address cas v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa h or l v oh v ol fpm2
semiconductor group 18 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram fast page mode read-modify-write cycle aaaa aaaa aaaa aaaa aa aa aa aa aaaa aaaa aaaa aaaa aa aa aa aa aaaa aaaa aaaa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aaaa aaaa aaaa a a a aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aaaa aaaa aaaa a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aaaa aaaa aaaa a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa t cah t cp t dzc t dzo t rac t cac t clz t rcs t aa t oea t rcd t rad t rah t asr t asc t cas t cas t prwc t cwd t cah t asc t cas t rsh t rp t crp t asr t cah t asc t ral t cwd t rwd t cwl t cwl t cwd t awd t awd t wp t wp t cwl t rwl t awd t wp t odd t oeh t dh t ds t cpa t oez t clz t dzc t aa t cac t oea t ds t oez t dh t oeh t aa t odd t dzc t cpa t oea t clz t ds t dh t oeh t odd ras v ih v il cas v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol we oe address i/o (inputs) i/o (outputs) data in data in data in data out out data data out row column address column row t ras t csh column t cpwd t cpwd aaaa a aaa a aaa a aaa a aaa a aaa a aaa aaaa aaa aa a aa a aa a aa a aa a aa a aaa h or l t oez
semiconductor group 19 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram ras -only refresh cycle aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa t crp t rah t rp t ras t rc t asr t asr t rpc v ih v il v ih v il v ih v il v oh v ol row row hi-z address ras cas i/o (outputs) aaaa a aaa a aaa a aaa a aaa a aaa aaaa aaaa aaa a aaa a aaa a aaa a aaa a aaaa h or l wl9
semiconductor group 20 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram self refresh aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa t rps t rass t rp t crp t cp t rpc t wrh t wrp t csr t off t oez t cdd t odd v ih v il v ih v il v ih v il v ih v il v ih v il hi-z a aaa a aaa a aaa a aaa a aaa a aaa aaa a aaa a aaa a aaa a aaa a aaa a h or l ras i/o (outputs) i/o (inputs) oe we cas v oh v ol t chs wl13
semiconductor group 21 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram cas -before-ras refresh cycle aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa t rp t ras t rp t rc t crp t cp t rpc t chr t wrh t wrp t csr t rpc t off t oez t cdd t odd v ih v il v ih v il v ih v il v ih v il v ih v il hi-z aaaa a aaa a aaa a aaa a aaa a aaa aaaa aaaa aaa a aaa a aaa a aaa a aaa a aaaa h or l ras i/o (outputs) i/o (inputs) oe we cas v oh v ol wl10
semiconductor group 22 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram hidden refresh cycle (read) aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa ras i/o (outputs) i/o (inputs) oe we address cas t rc t rc t ras t ras t rp t rp t crp t chr t rad t cah t asc t rah t asr t asr t rcs t rrh t aa t dzc t dzo t cac t rac t clz t oez t off t odd t cdd t rcd t rsh t oea v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t wrp t wrh aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa h or l valid data out row column row hi-z v oh v ol wl11
semiconductor group 23 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram hidden refresh cycle (early write) aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa ras i/o (output) i/o (input) we address v ih v il v ih v il v ih v il cas v ih v il v ih v il aaaa a aaa a aaa a aaa a aaa a aaa aaaa aaa a aaa a aaa a aaa a aaa a h or l t rc t ras t rcd t rsh t rad t cah t wcs t wch t wp t asr t rah t ds t dh t asr t crp t chr t rp t ras t rc t rp t asc row row valid data hi-z column v oh v ol t wrp t wrh wl12
semiconductor group 24 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram cas -before-ras refresh counter test cycle aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa t csr t asr t asc t chr t cp t wrp t ral t cah t rsh t rp t ras t cas t rcs t cdd t cac t aa t wrh t oea t odd t clz t dzc t dzo t oez t off t rwl t cwl t wch t wcs t wrh t wrp t ds t dh v ih v il v ih v il v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il ras i/o (inputs) oe we address cas i/o (outputs) i/o (outputs) i/o (inputs) we oe column row data out data in hi-z read cycle: write cycle: t rrh t rch
semiconductor group 25 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram test mode entry aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa t rc t ras t rp t rpc t crp t chr t wth t rpc t rp t cp t csr t wts t cdd t off t oez t odd i/o (outputs) v oh v ol v ih v il v ih v il i/o (inputs) oe we v ih v il cas ras v ih v il v ih v il a aaa a aaa a aaa a aaa a aaa a aaa aaa a aaa a aaa a aaa a aaa a aaa a h or l hi-z address aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa t rah t asr v ih v il row wl15 hi-z
semiconductor group 26 hyb 3116(7)400bj/bt(l) -50/-60/-70 3.3v 4mx4-dram package outlines plastic package p-soj-26/24-1 (300 mil) (small outline j-leads, smd) 1) does not include plastic or metal protrusion of 0.15 max per side index marking gpj05628 plastic package p-tsopii-26/24-1 (300mil) (thin small outline package, smd) 1) does not include plastic or metal protrusion of 0.15 max. per side 24x 0.2 m - 0. 0 3 -0.1 -0.2 0.6 0.1 1) index marking 0.15 max. 9.22 1 1.27 max. 13 1 14 26 +0 . 0 6 0 . 1 5 7.62 +0.12 0.4 1.27 17.27 0.05 - + 0.2 - + 0.13 - + 5 max. o -0.25 gpx05857

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